Non-volatile memory with test rows for disturb detection
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United States of America Patent
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-
Feb 8, 2005
Grant Date -
Aug 28, 2003
app pub date -
Feb 14, 2003
filing date -
Aug 30, 2001
priority date (Note) -
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Abstract
A non-volatile memory device has an array of memory cells arranged in rows and columns. The memory cells can be externally accessed for programming, erasing and reading operations. Test rows of memory cells are provided in the array to allow for memory cell disturb conditions. The test rows are not externally accessible for standard program and read operations. The test rows are located near bit line driver circuitry to insure the highest exposure to bit line voltages that may disturb memory cells in the array.
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