Shift register implementations of first-in/first-out memories utilizing a double increment gray code counter
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United States of America Patent
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Feb 15, 2005
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N/A
app pub date -
Jan 16, 2001
filing date -
Apr 28, 2000
priority date (Note) -
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Abstract
First-in/first-out ('FIFO') memory circuitry includes first and second Gray-code-based counters for respectively counting write and read clock signals. A Gray code subtractor subtracts from one another the counts output by the counters. Shift register circuitry shifts in successive data words in synchronism with the write clock signal. The shift register circuitry includes selection circuitry configured to select one of the data words based on a Gray code decoding of information from the subtractor. Circuitry may also be included to monitor the information from the subtractor to detect full or empty conditions of the shift register circuitry.
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