NAND type flash EEPROM in which sequential programming process is performed by using different intermediate voltages
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United States of America Patent
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Feb 22, 2005
Grant Date -
Jun 3, 2004
app pub date -
Apr 3, 2003
filing date -
Nov 29, 2002
priority date (Note) -
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Abstract
A nonvolatile semiconductor memory device includes a NAND memory cell array, booster circuit, row decoder, bit line control circuit and column decoder. In the device, the magnitude of intermediate voltage applied to the control gates of memory transistors from the booster circuit via the row decoder is changed according to the position of a selected control gate line when data is sequentially programmed into the memory transistors in the memory cell array. Alternatively, a plurality of different intermediate voltages are applied when data is simultaneously programmed into memory transistors connected to the selected control gate line.
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