US Patent No: 6,859,397

Number of patents in Portfolio can not be more than 2000

Source side self boosting technique for non-volatile memory

1 Status Updates

Stats

ALSO PUBLISHED AS: 20040174748
ATTORNEY / AGENT: (SPONSORED)
 

Importance

Loading Importance Indicators... loading....

Abstract

A non-volatile semiconductor memory system (or other type of memory system) is programmed in a manner that avoids program disturb. In one embodiment that includes a flash memory system using a NAND architecture, program disturb is avoided by increasing the channel potential of the source side of the NAND string during the programming process. One exemplar implementation includes applying a voltage (e.g. Vdd) to the source contact and turning on the source side select transistor for the NAND sting corresponding to the cell being inhibited. Another implementation includes applying a pre-charging voltage to the unselected word lines of the NAND string corresponding to the cell being inhibited prior to applying the program voltage.

Loading the Abstract Image... loading....

First Claim

Related Publications

Loading Related Publications... loading....

Patent Owner(s)

Patent OwnerAddressTotal Patents
SANDISK TECHNOLOGIES INC.PLANO, TX1506

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chen, Jian San Jose, CA 1002 7106
Higashitani, Masaaki Cupertino, CA 138 790
Li, Yan Milpitas, CA 536 3641
Lutze, Jeffrey W San Jose, CA 137 1054

Cited Art

Patent Info (Count) # Cites Year
 
KABUSHIKI KAISHA TOSHIBA (8)
6,134,157 Nonvolatile semiconductor memory device capable of preventing data from being written in error 15 1998
6,011,287 Non-volatile semiconductor memory device 102 1998
5,986,929 Multi-level nonvolatile semiconductor memory device 45 1998
6,108,238 Programmable semiconductor memory device having program voltages and verify voltages 45 1998
6,046,935 Semiconductor device and memory system 592 1999
6,307,807 Nonvolatile semiconductor memory 91 1999
6,363,010 Nonvolatile semiconductor memory device 58 2001
6,493,265 Nonvolatile semiconductor memory device 41 2002
 
SAMSUNG ELECTRONICS CO., LTD. (8)
5,677,873 Methods of programming flash EEPROM integrated circuit memory devices to prevent inadvertent programming of nondesignated NAND memory cells therein 97 1996
6,028,788 Flash memory device 32 1997
5,973,962 Method of programming non-volatile memory devices having a NAND type cell array 27 1998
6,061,270 Method for programming a non-volatile memory device with program disturb control 125 1998
6,353,555 Flash memory device capable of minimizing a substrate voltage bouncing and a program method thereof 55 2000
6,411,551 Multi-state nonvolatile semiconductor memory device which is capable of regularly maintaining a margin between threshold voltage distributions 21 2000
6,480,419 Bit line setup and discharge circuit for programming non-volatile memory 61 2001
6,469,933 Flash memory device capable of preventing program disturb and method for programming the same 52 2001
 
SANDISK TECHNOLOGIES INC. (3)
5,776,810 Method for forming EEPROM with split gate source side injection 85 1994
5,867,429 High density non-volatile flash memory without adverse effects of electric field coupling between adjacent floating gates 310 1997
6,456,528 Selective operation of a multi-state non-volatile memory system in a binary mode 508 2001
 
SPANSION LLC (3)
5,715,194 Bias scheme of program inhibit for random programming in a nand flash memory 98 1996
5,991,202 Method for reducing program disturb during self-boosting in a NAND flash memory 193 1998
6,228,782 Core field isolation for a NAND flash memory 6 1999
 
ABEDNEJA ASSETS AG L.L.C. (1)
5,748,538 OR-plane memory cell array for flash memory with bit-based write capability, and methods for programming and erasing the memory cell array 81 1996
 
TEXAS INSTRUMENTS INCORPORATED (1)
5,467,306 Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms 123 1993

Patent Citation Ranking

Forward Cites

Patent Info (Count) # Cites Year
 
SANDISK TECHNOLOGIES INC. (166)
7,161,833 Self-boosting system for flash memory cells 54 2004
7,170,793 Programming inhibit for non-volatile memory 22 2004
7,020,026 Bitline governed approach for program control of non-volatile memory 37 2004
7,307,884 Concurrent programming of non-volatile memory 7 2004
7,450,433 Word line compensation in non-volatile memory erase operations 7 2004
6,975,537 Source side self boosting technique for non-volatile memory 33 2005
7,295,478 Selective application of program inhibit schemes in non-volatile memory 9 2005
7,280,408 Bitline governed approach for programming non-volatile memory 9 2005
7,088,621 Bitline governed approach for coarse/fine programming 40 2005
7,286,406 Method for controlled programming of non-volatile memory exhibiting bit line coupling 5 2005
7,206,235 Apparatus for controlled programming of non-volatile memory exhibiting bit line coupling 22 2005
7,486,564 Soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 4 2005
7,408,804 Systems for soft programming non-volatile memory utilizing individual verification and additional soft programming of subsets of memory cells 53 2005
7,403,424 Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells 10 2005
7,400,537 Systems for erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells 7 2005
7,545,675 Reading non-volatile storage with efficient setup 4 2005
7,369,437 System for reading non-volatile storage with efficient setup 8 2005
7,436,703 Active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 6 2005
7,362,615 Methods for active boosting to minimize capacitive coupling effect between adjacent gates of flash memory devices 11 2005
7,466,590 Self-boosting method for flash memory cells 1 2005
7,499,319 Read operation for non-volatile storage with compensation for coupling 4 2006
7,436,733 System for performing read operation on non-volatile storage with compensation for coupling 17 2006
7,301,812 Boosting to control programming of non-volatile memory 6 2006
7,511,995 Self-boosting system with suppression of high lateral electric fields 2 2006
7,428,165 Self-boosting method with suppression of high lateral electric fields 0 2006
7,515,463 Reducing the impact of program disturb during read 6 2006
7,499,326 Apparatus for reducing the impact of program disturb 15 2006
7,436,713 Reducing the impact of program disturb 7 2006
7,426,137 Apparatus for reducing the impact of program disturb during read 7 2006
7,436,709 NAND flash memory with boosting 7 2006
7,286,408 Boosting methods for NAND flash memory 10 2006
7,457,163 System for verifying non-volatile storage using different voltages 28 2006
7,440,331 Verify operation for non-volatile storage using different voltages 33 2006
7,450,421 Data pattern sensitivity compensation using different voltage 37 2006
7,310,272 System for performing data pattern sensitivity compensation using different voltage 61 2006
7,391,650 Method for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates 4 2006
7,342,831 System for operating non-volatile memory using temperature compensation of voltages of unselected word lines and select gates 60 2006
7,492,633 System for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines 3 2006
7,349,261 Method for increasing programming speed for non-volatile memory by applying counter-transitioning waveforms to word lines 5 2006
7,489,549 System for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 11 2006
7,486,561 Method for non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 4 2006
7,440,326 Programming non-volatile memory with improved boosting 11 2006
8,189,378 Reducing program disturb in non-volatile storage 0 2006
8,184,478 Apparatus with reduced program disturb in non-volatile storage 0 2006
7,977,186 Providing local boosting control implant for non-volatile memory 0 2006
7,705,387 Non-volatile memory with local boosting control implant 1 2006
7,535,766 Systems for partitioned soft programming in non-volatile memory 3 2006
7,499,338 Partitioned soft programming in non-volatile memory 6 2006
7,499,317 System for partitioned erase and erase verification in a non-volatile memory to compensate for capacitive coupling 0 2006
7,495,954 Method for partitioned erase and erase verification to compensate for capacitive coupling effects in non-volatile memory 2 2006
7,691,710 Fabricating non-volatile memory with dual voltage select gate structure 0 2006
7,616,490 Programming non-volatile memory with dual voltage select gate structure 2 2006
7,586,157 Non-volatile memory with dual voltage select gate structure 0 2006
7,596,031 Faster programming of highest multi-level state for non-volatile memory 2 2006
7,468,911 Non-volatile memory using multiple boosting modes for reduced program disturb 52 2006
7,440,323 Reducing program disturb in non-volatile memory using multiple boosting modes 10 2006
7,696,035 Method for fabricating non-volatile memory with boost structures 3 2006
7,508,710 Operating non-volatile memory with boost structures 49 2006
7,508,703 Non-volatile memory with boost structures 1 2006
7,697,338 Systems for controlled boosting in non-volatile memory soft programming 3 2006
7,535,763 Controlled boosting in non-volatile memory soft programming 5 2006
7,623,386 Reducing program disturb in non-volatile storage using early source-side boosting 4 2006
7,623,387 Non-volatile storage with early source-side boosting for reducing program disturb 2 2006
7,471,566 Self-boosting system for flash memory cells 7 2006
7,570,520 Non-volatile storage system with initial programming voltage based on trial 50 2006
7,551,482 Method for programming with initial programming voltage based on trial 5 2006
7,616,498 Non-volatile storage system with resistance sensing and compensation 28 2006
7,590,002 Resistance sensing and compensation for non-volatile storage 27 2006
7,495,962 Alternating read mode 4 2006
7,468,918 Systems for programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data 11 2006
7,463,531 Systems for programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages 9 2006
7,450,430 Programming non-volatile memory with reduced program disturb by using different pre-charge enable voltages 7 2006
7,440,324 Apparatus with alternating read mode 48 2006
7,433,241 Programming non-volatile memory with reduced program disturb by removing pre-charge dependency on word line data 10 2006
7,583,535 Biasing non-volatile storage to compensate for temperature variations 5 2006
7,583,539 Non-volatile storage with bias for temperature compensation 2 2006
7,554,853 Non-volatile storage with bias based on selective word line 1 2006
7,525,843 Non-volatile storage with adaptive body bias 7 2006
7,468,919 Biasing non-volatile storage based on selected word line 8 2006
7,468,920 Applying adaptive body bias to non-volatile storage 6 2006
7,535,764 Adjusting resistance of non-volatile memory using dummy memory cells 8 2007
7,904,793 Method for decoding data in non-volatile storage using reliability metrics based on multiple reads 7 2007
7,797,480 Method for reading non-volatile storage using pre-conditioning waveforms and modified reliability metrics 1 2007
7,606,071 Compensating source voltage drop in non-volatile storage 6 2007
7,606,072 Non-volatile storage with compensation for source voltage drop 2 2007
7,606,079 Reducing power consumption during read operations in non-volatile storage 3 2007
7,440,327 Non-volatile storage with reduced power consumption during read operations 3 2007
7,463,522 Non-volatile storage with boosting using channel isolation switching 0 2007
7,460,404 Boosting for non-volatile storage using channel isolation switching 3 2007
7,706,189 Non-volatile storage system with transitional voltage during programming 3 2007
7,656,703 Method for using transitional voltage during programming of non-volatile storage 2 2007
7,545,678 Non-volatile storage with source bias all bit line sensing 0 2007
7,539,060 Non-volatile storage using current sensing with biasing of source and P-Well 0 2007
7,532,516 Non-volatile storage with current sensing of negative threshold voltages 0 2007
7,489,554 Method for current sensing with biasing of source and P-well in non-volatile storage 0 2007
7,471,567 Method for source bias all bit line sensing in non-volatile storage 6 2007
7,447,079 Method for sensing negative threshold voltages in non-volatile storage using current sensing 17 2007
7,599,224 Systems for coarse/fine program verification in non-volatile memory using different reference levels for improved sensing 7 2007
7,508,715 Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing 15 2007
7,522,457 Systems for erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage 1 2007
7,457,166 Erase voltage manipulation in non-volatile memory for controlled shifts in threshold voltage 4 2007
7,894,269 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells 3 2007
7,652,929 Non-volatile memory and method for biasing adjacent word line for verify during programming 9 2007
7,577,034 Reducing programming voltage differential nonlinearity in non-volatile storage 0 2007
7,894,263 High voltage generation and control in source-side injection programming of non-volatile memory 1 2007
7,447,086 Selective program voltage ramp rates in non-volatile memory 3 2007
7,561,473 System for performing data pattern sensitivity compensation using different voltage 3 2007
7,821,835 Concurrent programming of non-volatile memory 0 2007
7,796,444 Concurrent programming of non-volatile memory 0 2007
7,570,518 Concurrent programming of non-volatile memory 1 2007
7,411,827 Boosting to control programming of non-volatile memory 10 2007
7,688,638 Faster programming of multi-level non-volatile storage through reduced verify operations 2 2007
8,193,055 Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution 1 2007
7,723,186 Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 2 2007
7,463,528 Temperature compensation of select gates in non-volatile memory 2 2007
7,460,407 Temperature compensation of voltages of unselected word lines in non-volatile memory based on word line position 1 2007
7,468,921 Method for increasing programming speed for non-volatile memory by applying direct-transitioning waveforms to word lines 0 2008
7,606,100 Erasing non-volatile memory using individual verification and additional erasing of subsets of memory cells 1 2008
7,672,163 Control gate line architecture 2 2008
7,577,026 Source and drain side early boosting using local self boosting for non-volatile storage 0 2008
7,606,076 Sensing in non-volatile storage using pulldown to regulated source voltage to remove system noise 4 2008
7,915,664 Non-volatile memory with sidewall channels and raised source/drain regions 0 2008
8,051,240 Compensating non-volatile storage using different pass voltages during program-verify and read 1 2008
7,719,902 Enhanced bit-line pre-charge scheme for increasing channel boosting in non-volatile storage 0 2008
7,800,956 Programming algorithm to reduce disturb with minimal extra time penalty 3 2008
7,751,249 Minimizing power noise during sensing in memory device 2 2008
7,751,250 Memory device with power noise minimization during sensing 0 2008
7,876,611 Compensating for coupling during read operations in non-volatile storage 1 2008
7,843,739 System for verifying non-volatile storage using different voltages 1 2008
7,796,430 Non-volatile memory using multiple boosting modes for reduced program disturb 3 2008
7,755,946 Data state-based temperature compensation during sensing in non-volatile memory 2 2008
7,606,074 Word line compensation in non-volatile memory erase operations 1 2008
7,773,414 Self-boosting system for flash memory cells 0 2008
7,751,244 Applying adaptive body bias to non-volatile storage based on number of programming cycles 2 2008
7,633,802 Non-real time reprogramming of non-volatile memory to achieve tighter distribution of threshold voltages 51 2008
7,778,106 Read operation for non-volatile storage with compensation for coupling 1 2009
7,613,068 Read operation for non-volatile storage with compensation for coupling 3 2009
7,768,826 Methods for partitioned erase and erase verification in non-volatile memory to compensate for capacitive coupling effects 0 2009
7,796,433 Apparatus for reducing the impact of program disturb 0 2009
7,864,570 Self-boosting system with suppression of high lateral electric fields 0 2009
8,130,556 Pair bit line programming to improve boost voltage clamping 0 2009
8,004,900 Controlling select gate voltage during erase to improve endurance in non-volatile memory 0 2009
7,790,562 Method for angular doping of source and drain regions for odd and even NAND blocks 2 2009
7,733,701 Reading non-volatile storage with efficient setup 0 2009
7,768,834 Non-volatile storage system with initial programming voltage based on trial 1 2009
8,111,554 Starting program voltage shift with cycling of non-volatile memory 0 2009
8,284,606 Compensating for coupling during programming 0 2009
7,911,838 Read operation for non-volatile storage with compensation for coupling 0 2009
8,179,723 Non-volatile memory with boost structures 0 2010
7,911,846 Apparatus for reducing the impact of program disturb 0 2010
8,263,465 Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer 0 2010
7,911,849 Controlled boosting in non-volatile memory soft programming 1 2010
8,000,146 Applying different body bias to different substrate portions for non-volatile storage 0 2010
8,274,831 Programming non-volatile storage with synchronized coupling 1 2010
7,902,031 Method for angular doping of source and drain regions for odd and even NAND blocks 0 2010
8,383,479 Integrated nanostructure-based non-volatile memory fabrication 0 2010
8,014,205 System for verifying non-volatile storage using different voltages 0 2010
8,331,154 Apparatus for reducing the impact of program disturb 0 2011
8,270,217 Apparatus for reducing the impact of program disturb 0 2011
8,163,622 Method for angular doping of source and drain regions for odd and even NAND blocks 0 2011
8,406,052 High voltage generation and control in source-side injection programming of non-volatile memory 0 2011
8,199,571 Read operation for non-volatile storage with compensation for coupling 0 2011
8,400,839 Nonvolatile memory and method for compensating during programming for perturbing charges of neighboring cells 0 2011
8,427,873 Read operation for non-volatile storage with compensation for coupling 0 2011
8,164,957 Reducing energy consumption when applying body bias to substrate having sets of nand strings 0 2011
8,411,507 Compensating for coupling during programming 0 2012
 
SANDISK CORPORATION (16)
7,339,834 Starting program voltage shift with cycling of non-volatile memory 26 2005
7,230,854 Method for programming non-volatile memory with self-adjusting maximum program loop 9 2005
7,161,836 Method for programming non-volatile memory with self-adjusting maximum program loop 0 2005
7,023,737 System for programming non-volatile memory with self-adjusting maximum program loop 28 2005
7,218,552 Last-first mode and method for programming of non-volatile memory with reduced program disturb 14 2005
7,170,788 Last-first mode and apparatus for programming of non-volatile memory with reduced program disturb 36 2005
7,366,022 Apparatus for programming of multi-state non-volatile memory using smart verify 8 2005
7,301,817 Method for programming of multi-state non-volatile memory using smart verify 71 2005
7,430,138 Erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells 11 2005
7,403,428 Systems for erasing non-volatile memory utilizing changing word line conditions to compensate for slower erasing memory cells 4 2005
7,355,888 Apparatus for programming non-volatile memory with reduced program disturb using modified pass voltages 9 2005
7,355,889 Method for programming non-volatile memory with reduced program disturb using modified pass voltages 25 2005
7,206,231 System for programming non-volatile memory with self-adjusting maximum program loop 5 2006
7,492,634 Method for programming of multi-state non-volatile memory using smart verify 7 2007
7,633,812 Starting program voltage shift with cycling of non-volatile memory 0 2008
7,630,254 Starting program voltage shift with cycling of non-volatile memory 5 2008
 
MICRON TECHNOLOGY, INC. (15)
7,551,466 Bit line coupling 2 2006
7,606,075 Read operation for NAND memory 1 2006
7,433,231 Multiple select gates with non-volatile memory cells 60 2006
7,450,422 NAND architecture memory devices and operation 3 2006
7,755,939 System and devices including memory resistant to program disturb and methods of using, making, and operating the same 0 2008
7,800,947 Multiple select gates with non-volatile memory cells 0 2008
7,773,418 Non-volatile memory with both single and multiple level cells 1 2008
7,889,561 Read operation for NAND memory 0 2009
8,223,549 NAND flash memory programming 0 2009
7,965,548 Systems and devices including memory resistant to program disturb and methods of using, making, and operating the same 0 2010
8,000,136 Non-volatile memory with both single and multiple level cells 1 2010
7,995,391 Multiple select gates with non-volatile memory cells 0 2010
8,305,810 Multiple select gates with non-volatile memory cells 0 2011
8,199,572 Non-volatile memory with both single and multiple level cells 0 2011
8,437,186 Non-volatile memory with both single and multiple level cells 0 2012
 
KABUSHIKI KAISHA TOSHIBA (7)
7,355,887 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 3 2005
7,365,018 Fabrication of semiconductor device for flash memory with increased select gate width 5 2005
7,672,158 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 0 2008
7,983,086 NAND flash memory 0 2009
7,940,562 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 0 2010
8,363,467 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control 0 2011
8,159,880 NAND flash memory 0 2011
 
SANDISK IL LTD. (5)
7,679,965 Flash memory with improved programming precision 1 2007
7,660,166 Method of improving programming precision in flash memory 1 2007
8,073,648 Measuring threshold voltage distribution in memory using an aggregate characteristic 0 2007
7,613,045 Operation sequence and commands for measuring threshold voltage distribution in memory 1 2007
7,952,928 Increasing read throughput in non-volatile memory 0 2008
 
ROUND ROCK RESEARCH, LLC (4)
7,345,924 Programming memory devices 28 2006
7,505,323 Programming memory devices 2 2008
7,688,630 Programming memory devices 1 2009
8,174,889 Programming memory devices 0 2010
 
HYNIX SEMICONDUCTOR INC. (3)
7,643,338 Method for programming a flash memory device 2 2006
7,589,996 Method for programming a flash memory device 0 2006
7,944,752 Method for programming a flash memory device 0 2009
 
SAMSUNG ELECTRONICS CO., LTD. (3)
7,596,022 Method for programming a multi-level non-volatile memory device 7 2007
7,508,705 Method for programming a multi-level non-volatile memory device 5 2007
7,889,567 Nonvolatile memory device for preventing program disturbance and method of programming the nonvolatile memory device 1 2008
 
SANDICK TECHNOLOGIES INC. (1)
8,406,063 Programming non-volatile storage with synchonized coupling 0 2012
 
SPANSION LLC (1)
7,791,947 Non-volatile memory device and methods of using 0 2008
 
STMICROELECTRONICS S.R.L. (1)
7,212,439 NAND flash memory device and method of programming the same 3 2004
 
UNITED MICROELECTRONICS CORP. (1)
7,123,518 Memory device 9 2004

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
11.5 Year Payment $7400.00 $3700.00 $1850.00 Aug 22, 2016
Fee Large entity fee small entity fee micro entity fee
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00