Digital signal processor computation core with pipeline having memory access stages and multiply accumulate stages positioned for efficient operation
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United States of America Patent
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Feb 22, 2005
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N/A
app pub date -
May 12, 2000
filing date -
May 12, 1999
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Abstract
A computation core includes a computation block, an addressing block and an instruction sequencer, which are coupled to a memory through a memory interface. The computation block includes a register file and dual execution units. The execution units include features for enhanced performance in executing digital signal computations. The computation core is configured for executing digital signal processor instructions and microcontroller instructions, while achieving efficient digital signal processor computation and high code density. A finite impulse response filter algorithm achieves high performance on the dual execution units.
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