Method and apparatus for built-in self-test of logic circuits with multiple clock domains
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United States of America Patent
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Mar 1, 2005
Grant Date -
Sep 11, 2003
app pub date -
Mar 7, 2002
filing date -
Mar 7, 2002
priority date (Note) -
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Abstract
A system for remotely/automatedly testing an ASIC and particularly to testing a user-designed circuit is disclosed. In general, a system in accordance with the invention includes a plurality of cells, where the cells are couplable to form a user-designed circuit, e.g., by customizing routing. Within the ASIC and prior to any knowledge of the user-designed circuit, the ASIC includes circuitry to enable internal remote/automated testing of the user-designed circuit to be later formed. The circuitry controls the input and mode of operation of the cells and the sequencing of multiple synchronous or asynchronous clock domain inputs thereby providing testing of the user-designed circuit at speed for stuck-at-faults and delay faults.
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