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Abstract

A memory (10) includes a variable refresh control circuit (20) for controlling the refresh rate of a memory array (12) using a capacitor for data storage. In one embodiment, each test cell of a plurality of test memory cells (30, 32, 34, and 36) is refreshed at different rates. A monitor circuit (18) is provided for monitoring the stored logic state of each of the plurality of test memory cells, and in response, adjusting the refresh rate of the memory array (12). In another embodiment, a variable refresh control circuit (20') includes a plurality of test memory cells (70, 72, 74, and 76) that are all refreshed at the same rate but each of the test memory cells (70, 72, 74, and 76) is implemented to have a different charge storage capacity than the other test memory cells. The monitor circuit (18) monitors the stored logic state of each of the plurality of test memory cells (70, 72, 74, and 76), and in response, adjusts a refresh rate of the memory array (12).

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First Claim