Method and system for network processor scheduling outputs based on multiple calendars

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6862292
SERIAL NO

09548910

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
INTERNATIONAL BUSINESS MACHINES CORPORATIONARMONK, NY46918

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Bass, Brian Mitchell Apex, NC 60 1543
Calvignac, Jean Louis Cary, NC 108 2268
Heddes, Marco C Raleigh, NC 78 1804
Siegel, Michael Steven Raleigh, NC 72 2135
Verplanken, Fabrice Jean La Gaude, FR 105 1795

Cited Art Landscape

Patent Info (Count) # Cites Year
 
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CHARTOLEAUX KG LIMITED LIABILITY COMPANY (1)
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ERICSSON AB (1)
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LUCENT TECHNOLOGIES INC. (1)
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HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP (1)
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SIEMENS AKTIENGESELLSCHAFT (1)
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SIEMENS GROUP SERVICES LIMITED (1)
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CISCO TECHNOLOGY, INC. (2)
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ALCATEL-LUCENT CANADA INC. (1)
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THE BOARD OF TRUSTEES OF THE LELAND STANFORD JUNIOR UNIVERSITY (1)
5923644 Apparatus and method for processing multicast cells in an input-queued multicast switch 44 1996
 
XEROX CORPORATION (2)
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Telesis Technologies Laboratory (1)
5917822 Method for providing integrated packet services over a shared-media network 221 1996
 
FUJITSU LIMITED (2)
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5940375 Feedback control apparatus and cell scheduling apparatus for use with cell exchange 36 1997
 
MOTOROLA, INC. (1)
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PROVENANCE ASSET GROUP LLC (1)
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ALCATEL CANADA INC. (1)
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INTEL CORPORATION (1)
5959993 Scheduler design for ATM switches, and its implementation in a distributed shared memory architecture 37 1996
 
National Science Foundation (1)
5923656 Scalable broad band input-queued ATM switch including weight driven cell scheduler 72 1996
 
AVAYA INC. (1)
* 6438106 Inter-class schedulers utilizing statistical priority guaranteed queuing and generic cell-rate algorithm priority guaranteed queuing 86 1998
 
KABUSHIKI KAISHA TOSHIBA (2)
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* 6101193 Packet scheduling scheme for improving short time fairness characteristic in weighted fair queueing 98 1997
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
SLT LOGIC LLC (2)
* 7228375 System and method for efficient input/output of a computer system 7 2002
* 7228550 System and method for making communication streams available to processes executing under control of an operating system but without the intervention of the operating system 6 2003
 
Other [Check patent profile for assignment information] (1)
* 2008/0301,406 SYSTEM AND METHOD FOR ALLOCATING COMMUNICATIONS TO PROCESSORS IN A MULTIPROCESSOR SYSTEM 47 2008
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 8072972 Configurable hardware scheduler calendar search algorithm 0 2006
* 2007/0204,114 Configurable Hardware Scheduler Calendar Search Algorithm 0 2006
 
RPX CLEARINGHOUSE LLC (2)
* 7369491 Regulating data-burst transfer 26 2003
* 7817543 Regulating data-burst transfer 17 2008
 
AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. (2)
* 7136381 Memory management unit architecture for switch fabric 24 2001
* 2002/0012,341 Memory management unit architecture for switch fabric 3 2001
* Cited By Examiner