Clock reproduction circuit
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United States of America Patent
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-
Mar 1, 2005
Grant Date -
Apr 1, 2004
app pub date -
Aug 13, 2003
filing date -
Feb 27, 2001
priority date (Note) -
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status (Latency Note)
Importance
Abstract
A master clock signal source (10) generates a master clock signal having a frequency equal to N times the bit rate of received data, where N is a positive integer. A modulo-N counter (12) counts the master clock signal. An edge detecting circuit (4) detects a transition of the received data from a H level to a L level. A counter (8) counts the master clock signal and resets the modulo-N counter (12) if the count counted during a time period in which three edge representative signals occur is 2N. In accordance with the count in the modulo-N counter 12, a clock generating unit 14 generates a clock signal.
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