Three input variable subfield comparation for fast matching
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United States of America Patent
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Mar 8, 2005
Grant Date -
Jun 12, 2003
app pub date -
Dec 10, 2001
filing date -
Dec 10, 2001
priority date (Note) -
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status (Latency Note)
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Abstract
The relationship between a sum of applied address operands and a matching virtual page number is exploited to minimize the adder size required for fast number comparison. In one embodiment, variably-sized addresses are accommodated by augmenting a portion of the applied address operands to ensure easy access to potential carry bits. A comparator is used for each virtual page number stored in a translation look-aside buffer to quickly determine whether that virtual page number matches the applied address operand sum.
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