Diamond metal-filled patterns achieving low parasitic coupling capacitance
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United States of America Patent
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Mar 15, 2005
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app pub date -
Dec 19, 2002
filing date -
Dec 19, 2002
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Abstract
Provided are methods and composition for forming diamond metal-filled patterns above an integrated circuit substrate. A metal layer is formed above the integrated circuit substrate, which is then patterned such that a metal line is created. A plurality of diamond-shaped metal regions are then formed at least one of above and adjacent to the metal line formed on the integrated circuit substrate such that the density of metal on the integrated circuit substrate is greater than a specified density, thereby ensuring that a surface of dielectric formed above the metal line remains substantially planar after application of CMP to the dielectric layer.
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