Power-on state machine implementation with a counter to control the scan for products with hard-BISR memories
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United States of America Patent
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-
Mar 22, 2005
Grant Date -
Oct 16, 2003
app pub date -
Apr 11, 2002
filing date -
Apr 11, 2002
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An apparatus comprising a controller circuit and a BISR assembly circuit. The controller circuit may be configured to present one or more control signals. The control signals may be configured to control one or more built-in self-test (BIST) and built-in self-repair (BISR) modes of operation. The BISR assembly circuit generally comprises one or more memory blocks each comprising a counter configured to generate a clock cycle count value in response to a repair solution during the BIST and BISR operations. The memory blocks may be remapped in response to the count values during one or more of the BISR operations.
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