Coordinated recalibration of high bandwidth memories in a multiprocessor computer
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United States of America Patent
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Mar 29, 2005
Grant Date -
Sep 5, 2002
app pub date -
Mar 5, 2001
filing date -
Mar 5, 2001
priority date (Note) -
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Abstract
Methods and apparatus for implementing high-bandwidth memory subsystems in a multiprocessor computing environment. Each component in the memory subsystem has a recalibration procedure. The computer provides a low-frequency clock signal with a period substantially equal to the duration between recalibration cycles of the components of the memory subsystem. Transitions in the low-frequency clock signal initiate a deterministically-determined delay. Lapse of the delay in turn triggers the recalibration of the components of the memory subsystem, ensuring synchronous recalibration. Synchronizing the recalibration procedures minimizes the unavailability of the memory subsystems, consequently reducing voting errors between CPUs.
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