Stereolithographic methods for forming a protective layer on a semiconductor device substrate and substrates including protective layers so formed
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United States of America Patent
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Apr 5, 2005
Grant Date -
N/A
app pub date -
Jun 8, 2000
filing date -
Jun 8, 2000
priority date (Note) -
Expired
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Abstract
A stereolithographic method of applying material to form a protective layer on a preformed semiconductor die with a high degree of precision, either in the wafer stage, when attached to a lead frame, or to a singulated, bare die. The method is computerized and may utilize a machine vision feature to provide precise die-specific alignment. A semiconductor die may be provided with a protective structure in the form of at least one layer or segment of dielectric material having a controlled thickness or depth and a very precise boundary. The layer or segment may include precisely sized, shaped and located apertures through which conductive terminals, such as bond pads, on the surface of the die may be accessed. Dielectric material may also be employed as a structure to mechanically reinforce the die-to-lead frame attachment.
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