Unified exception handling for hierarchical multi-interrupt architectures
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United States of America Patent
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Apr 12, 2005
Grant Date -
Jun 13, 2002
app pub date -
Dec 13, 2000
filing date -
Dec 13, 2000
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A unified interrupt handling system and method is provided for an embeddable processor having multiple interrupt types. An instruction is inserted into the first vector address that disables the second interrupt mode. At the second vector address, an other instruction is inserted that branches to a common interrupt dispatcher. The common interrupt dispatcher is provided with an interrupt routine that processes the interrupt, and then re-enables the second interrupt modes. Interrupt requests are then processed by the common interrupt dispatcher without interruption.
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