Sharing a second tier cache memory in a multi-processor
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United States of America Patent
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Apr 12, 2005
Grant Date -
Jan 9, 2003
app pub date -
Mar 25, 2002
filing date -
Jul 6, 2001
priority date (Note) -
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Abstract
A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in the set of first tier cache memory. The second tier cache memory includes a data ring interface and a snoop ring interface.
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