Component connections using bumps and wells

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 6881609
APP PUB NO 20040101993A1
SERIAL NO

10701888

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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This specification describes techniques for fabricating connections between pairs of components. Each connection includes an array of bumps on a male component, and a matching array of wells filled with bonding material on a female component. The bump/well connections can be spaced with a pitch of less than 100 microns. One application of the invention is the attachment of electronic components to interconnection circuits or circuit assemblies to form electronic modules. The electronic components may be IC chips or high-density interconnect cables. Another application is alignment of optical components. The direct chip attachment techniques are described in the context of fabrication, assembly, test, rework, and cooling of electronic modules employing flip chip components. The preferred method is to fabricate the module on a glass carrier using a release layer so that the carrier can be removed after most of the processing is done.

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Patent Owner(s)

Patent OwnerAddress
HYNIX SEMICONDUCTOR INCGYEONGGI DO SOUTH KOREA GYEONGGI-DO

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Salmon, Peter C 200 E. Dana St., #8, Mountain View, CA 94041 74 1223

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