Lead frame and semiconductor package having a groove formed in the respective terminals for limiting a plating area
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United States of America Patent
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Apr 19, 2005
Grant Date -
Oct 17, 2002
app pub date -
Mar 21, 2002
filing date -
Mar 30, 2001
priority date (Note) -
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Abstract
A lead frame used for the production of a semiconductor package, wherein each of terminals of the lead frame to be wire-bonded to electrodes provided on the top surface of the semiconductor device has one or two groove(s) for limiting a plating area of noble metal. Since grooves are provided in each terminal, the accuracy of the plating area can be easily checked visually. Further, the grooves absorb stress applied to the terminal when the molded semiconductor packages are individually separated from each other by punching or dicing, and the situation where molding compound comes off of the terminal is prevented. In addition, since the grooves absorb vibrational stress applied to the terminal after mounting a semiconductor on the printed circuit board, the reliability of assembly is improved.
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