Semiconductor test apparatus
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United States of America Patent
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Apr 26, 2005
Grant Date -
Jul 29, 2004
app pub date -
Nov 12, 2003
filing date -
May 25, 2001
priority date (Note) -
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Abstract
There is disclosed a semiconductor test apparatus enabling writing into an information write space of a block including a failure cell into which block writing is inhibited partially or entirely by the bad block mask function and the fail loop back function. A pattern generation block outputs to an output controller a release signal (S4) for releasing the write inhibit instruction defined by an inhibit signal (S3) and a mask signal (SI). When the output controller receives the release signal (S4), the output controller outputs a write enable signal (WE) to an MUT (4).
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