Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same
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United States of America Patent
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May 3, 2005
Grant Date -
Aug 21, 2003
app pub date -
Feb 6, 2002
filing date -
Feb 6, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A three-dimensional (3-D) integrated chip system is provided with a first wafer including one or more integrated circuit (IC) devices; a second wafer including one or more integrated circuit (IC) devices; and metallic lines deposited on opposing surfaces of the first and second wafers at designated locations with an interlevel dielectric (ILD) recess surrounding the metallic lines to facilitate direct metal bonding between the first and second wafers and establish electrical connections between active IC devices on the first and second wafers.
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