Junction-isolated depletion mode ferroelectric memory devices
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United States of America Patent
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May 3, 2005
Grant Date -
Feb 3, 2005
app pub date -
Aug 26, 2004
filing date -
Aug 31, 2000
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Abstract
Depletion mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
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