Method and apparatus for localizing faults within a programmable logic device
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United States of America Patent
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May 3, 2005
Grant Date -
N/A
app pub date -
Oct 25, 2002
filing date -
Oct 25, 2002
priority date (Note) -
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Abstract
Method and apparatus for localizing faults within an integrated circuit is described. For example, a programmable logic device (PLD) is configured with a test pattern. A test stimulus is applied to the test pattern. State data responsive to the test pattern is obtained. The state data may be obtained from a readback datastream generated by the PLD. The expected state data may be generated by a second PLD that is known to contain no faults. The state data is compared with expected state data to produce difference information. The difference information is used, or more particularly is iteratively generated, to localize a fault or faults within a unit under test.
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