Edge synchronized phase-locked loop circuit
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United States of America Patent
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May 10, 2005
Grant Date -
May 20, 2004
app pub date -
Nov 15, 2002
filing date -
Nov 15, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
A phase-locked loop circuit for synchronizing an edge of an output signal with an edge of an input signal. The circuit detects an edge of an input clock signal, and a corresponding edge on an output signal. If the output signal edge is out of phase with the input clock edge, the circuit shifts the output signal by 180 degrees to effectively produce a single double-length clock phase. The synchronized phase-locked loop circuit provides predictable phase-locked loop output phase synchronization with an input clock.
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