Semiconductor memory device
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United States of America Patent
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May 10, 2005
Grant Date -
Sep 9, 2004
app pub date -
Jul 12, 2002
filing date -
Jul 17, 2001
priority date (Note) -
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Abstract
A semiconductor memory device having a first memory including a bit line, a word line arranged to intersect with the bit line and a storage unit arranged between the bit line and the word line, and a second memory different in type from the first memory. The first memory and the second memory are formed on a semiconductor substrate in a stacked manner reducing the thickness in the height direction and attaining further miniaturization (thinning). Further, no wire having a large parasitic capacitance or solder is employed for connecting the first memory and the second memory, thereby enabling high-speed data transfer between the first memory and the second memory.
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