Delay line and output clock generator using same
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United States of America Patent
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May 10, 2005
Grant Date -
N/A
app pub date -
Sep 3, 2003
filing date -
Sep 3, 2003
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A delay line for an adjustable, high speed clock generator is based on two-stage multiplexing, in which for all pairs of adjacent taps, a change from a current tap to an adjacent tap in the pair is executed by switching only one of the first stage and second stage multiplexers. Control signals are generated for the first and second stage multiplexers by logic based on bidirectional shift registers. The delay line is suitable for generation of an output clock having an adjustable phase, allowing for smooth, glitch-free adjustment over a large range of phases.
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