Method for applying instructions to microprocessor in test mode
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United States of America Patent
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May 10, 2005
Grant Date -
N/A
app pub date -
Oct 5, 2001
filing date -
Oct 26, 2000
priority date (Note) -
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status (Latency Note)
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Abstract
A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.
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