Multilevel semiconductor memory, write/read method thereto/therefrom and storage medium storing write/read program
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United States of America Patent
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May 17, 2005
Grant Date -
Mar 18, 2004
app pub date -
Aug 19, 2003
filing date -
Sep 18, 1996
priority date (Note) -
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Abstract
A method of reading data from a plurality of multi-level memory cells. The cells are arranged to correspond to a physical address space, each cell having at least one transistor. Each cell stores 2n levels of data. A logical address is converted into a physical address included in the physical address space. A determination is made whether a logical address space including the logical address matches the physical address space. The most significant bit (X1) is specified by comparing an output voltage of the transistor corresponding to the most significant bit with a reference voltage when a logical address space matches the physical address space. The specified bit is output from one of the cells corresponding to the physical address. A computer readable medium stores program code for carrying out the method of reading out the plurality of multi-level memory cells.
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