Method and arrangement for layout of gridless nonManhattan semiconductor integrated circuit designs
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United States of America Patent
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May 17, 2005
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N/A
app pub date -
Oct 5, 2001
filing date -
Jun 3, 2001
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Abstract
The present invention introduces several methods for laying out integrated circuit designs that use gridless non Manhattan routing to connect the integrated circuit components. In one embodiment, the non Manhattan routed integrated circuit designs are laid out by creating an initial route and then compacting the design down. In another embodiment, gridless non Manhattan integrated circuits are laid out by adapting a gridless Manhattan routing system into a gridless non Manhattan routing system by rotating a plane of a tile based maze router.
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