Clock synchronized dynamic memory and clock synchronized integrated circuit
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United States of America Patent
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May 24, 2005
Grant Date -
Jun 20, 2002
app pub date -
Aug 7, 2001
filing date -
Dec 19, 2000
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A synchronous dynamic memory has a clock input buffer receiving an external clock and outputting an input external clock, a command input buffer receiving commands, an address input buffer receiving addresses, and a data input buffer receiving data. During normal operation mode, the clock input buffer supplies the clock to the command, address, and data input buffers. During data hold modes, such as power down mode, the clock input buffer supplies the clock to the command input buffer but not to the address and data input buffers.
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