Multi-tiered memory bank having different data buffer sizes with a programmable bank select
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United States of America Patent
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May 24, 2005
Issued Date -
N/A
app pub date -
Aug 11, 2003
filing date -
Mar 31, 2000
priority date (Note) -
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Abstract
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
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