Importance

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Abstract

The digital phase control circuit of the present invention is provided with: voltage-controlled delay line VCDL1 in which differential buffers G1-G10 having a propagation delay time of 160 ps are concatenated in a plurality of stages; voltage-controlled delay line VCDL2 in which differential buffers H1-H8 having a propagation delay time of 200 ps are concatenated in a plurality of stages; selector S2 that extracts a clock signal from any stage of voltage-controlled delay line VCDL1 and outputs to the first stage of voltage-controlled delay line VCDL2; and selector S3 that extracts and outputs a clock signal from any stage of voltage-controlled delay line VCDL2. This digital phase control circuit 10 feedback-controls voltage-controlled delay line VCDL1 and voltage-controlled delay line VCDL2 by delay locked loops DLL1 and DLL2, controls the phases of clock signals with the difference 40 ps between 160 ps and 200 ps as the resolution; and therefore is a power-saving, compact, and high-resolution digital phase control circuit that suppresses increase in power consumption and increase in the area occupied by circuits to a minimum.

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First Claim