Dynamically programmable integrated switching device using an asymmetric 5T1C cell
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United States of America Patent
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May 31, 2005
Grant Date -
Jun 6, 2002
app pub date -
Dec 4, 2000
filing date -
Dec 4, 2000
priority date (Note) -
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Abstract
A switching element including first, second and third ports each comprising a plurality of lines is disclosed. A first memory cell includes a storage element, a first pass gate for selectively coupling a first line of the first port to the storage element, a second pass gate for selectively coupling a first line of the second port to the storage element, and a third pass gate for selectively coupling a first line of the third port to the storage element. A second memory cell includes a storage element, a first gate for selectively coupling a second line of the first port to the storage element, a second pass gate for selectively coupling a second line of the second port to the storage element, and a third pass gate for selectively coupling a second line of the third port to the storage element.
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