Floating point multiplier/accumulator with reduced latency and method thereof
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United States of America Patent
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Jun 7, 2005
Grant Date -
Feb 27, 2003
app pub date -
Aug 24, 2001
filing date -
Aug 24, 2001
priority date (Note) -
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Abstract
A circuit (10) for multiplying two floating point operands (A and C) while adding or subtracting a third floating point operand (B) removes latency associated with normalization and rounding from a critical speed path for dependent calculations. An intermediate representation of a product and a third operand are selectively shifted to facilitate use of prior unnormalized dependent resultants. Logic circuitry (24, 42) implements a truth table for determining when and how much shifting should be made to intermediate values based upon a resultant of a previous calculation, upon exponents of current operands and an exponent of a previous resultant operand. Normalization and rounding may be subsequently implemented, but at a time when a new cycle operation is not dependent on such operations even if data dependencies exist.
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