Importance

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Abstract

In integrated circuit (IC) devices, skew concerns between the clock pulses supplied to different latches hinder high speed operation. An IC device therefor includes a first clock processor means to generate a third clock pulse in response to first and second clock pulses with identical phase and frequency, a second clock processor means to generate a fifth clock pulse in response the third clock pulse and a fourth clock pulse with identical phase and frequency, and first and second latch groups each including a plurality of latches, in which the second clock pulse is generated via a buffer or divider from the third clock pulse, a fourth clock pulse is generated via a buffer or divider from the fifth clock pulse, and the third and fifth clock pulses are supplied to the first and second latch groups via a buffer, respectively.

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First Claim