FFT address generation method and apparatus
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United States of America Patent
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Jun 14, 2005
Grant Date -
N/A
app pub date -
Mar 26, 2002
filing date -
Feb 20, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method and apparatus are used to generate FFT data addresses based upon a computation stage value and a computation step value within that computation stage. The method includes the steps of generating a first data address by insertion at a bit insertion position a first bit between existing bits of a binary word and generating a second data address by inserting at the bit insertion position a second bit between existing bits of the binary word, wherein the binary word represents the computation step value. The apparatus includes a series of consecutive bit cells that generate the desired data addresses based upon a decoded value of the computation stage.
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