Method and apparatus for improving timing margin in an integrated circuit as determined from recorded pass/fail indications for relative phase settings
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United States of America Patent
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Jun 21, 2005
Issued Date -
N/A
app pub date -
Nov 5, 2001
filing date -
Dec 31, 1999
priority date (Note) -
Expired
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Abstract
Under the control of a processor executing a program, the timing margin of an electronic system can be improved by a series of operations that set the relative phase of receive and distributed clock signals from a number of given values, a relative phase of transmit and distributed clock signals from a number of given values, instruct an integrated circuit (IC) die to drive a sequence of outgoing data symbols and receive a sequence of incoming data symbols at those relative phase settings, and compares the outgoing symbols to the incoming symbols. A result of the comparison is recorded. The operations are repeated for other combinations of the discrete transmit and receive phase values. The relative phases are then set to a pair of values taken from the discrete transmit and receive phase values, which are closest to yielding a balanced timing margin as determined from the results of the comparisons.
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