Methods for fabricating semiconductor device test apparatus that include protective structures for intermediate conductive elements

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United States of America Patent

PATENT NO 6913988
SERIAL NO

10396844

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Abstract

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A method for fabricating apparatus for testing semiconductor devices includes forming protective structures for bond wires or other intermediate conductive elements thereof by sequentially fabricating one or more material layers. After a first layer is formed, each subsequent layer is superimposed upon, contiguous with, and mutually adhered to an underlying layer of the protective structure. In addition, a fence member may be assembled with or formed on the test substrate to align and receive a semiconductor device and, thereby, to facilitate assembly of the semiconductor device with the test substrate. The fence member can be formed integrally with the protective structures or secured over the protective structures. Stereolithographic processes may be used to fabricate the fence member.

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Patent Owner(s)

Patent OwnerAddress
MICRON TECHNOLOGY INCBOISE ID 83716-9632

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Akram, Salman Boise, ID 801 30978

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