Phase locked loop circuit using fractional frequency divider
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United States of America Patent
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-
Jul 5, 2005
Grant Date -
Jan 22, 2004
app pub date -
Jul 16, 2003
filing date -
Jul 19, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
Phase-locked loop (PLL) circuits include first and second PLL stages and use fractional frequency division. In one implementation, the first stage includes a voltage-controlled oscillator (VCO) whose output is provided to both first and second fractional frequency dividers. The output of the first frequency divider is provided to a first phase comparator whose output passes through a filter so as to provide the deviation signal that controls the output frequency of the first VCO. The output of the second fractional frequency divider is received by the second PLL stage as a reference signal.
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