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Abstract

A technique to provide a higher resolution DAC architecture for converting an N-bit digital word to a corresponding analog voltage signal without increasing chip area and switching capacitance. In one example embodiment, this is accomplished by using a triple string converter. In the triple string converter, a triple switching tree is coupled to a triple resistor string and to an analog output. Each switching tree includes a plurality of switches and each resistor string includes a plurality of corresponding resistors. A logic decoder coupled to the triple switching tree receives an N-bit digital word and generates a digital signal. The plurality of switches in each switching tree is substantially simultaneously controlled by the digital signal to output a range of corresponding analog voltage signals when the triple resistor string is connected across a voltage supply.

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First Claim