Method and arrangement for layout and manufacture of nonmanhattan semiconductor integrated circuit using simulated Euclidean wiring
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United States of America Patent
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Jul 5, 2005
Issued Date -
N/A
app pub date -
Oct 5, 2001
filing date -
Jun 3, 2001
priority date (Note) -
Expired
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Abstract
The present invention introduces several methods for implementing arbitrary angle wiring layers for integrated circuit manufacture with simulated Euclidean wiring. Entire routing layers may be implemented with arbitrary angle preferred wiring using simulated Euclidean wiring. In a first embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and vertical interconnect wire segments. In another embodiment, the arbitrary angle wiring layers are created by routing arbitrary angle wires created from a selected ratio alternating segments of horizontal interconnect wire segments and diagonal interconnect wire segments.
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