Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing
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United States of America Patent
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Jul 12, 2005
Grant Date -
Aug 26, 2004
app pub date -
Aug 29, 2003
filing date -
Feb 25, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.
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