Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice
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United States of America Patent
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Jul 12, 2005
Grant Date -
Sep 16, 2004
app pub date -
Mar 12, 2003
filing date -
Mar 12, 2003
priority date (Note) -
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status (Latency Note)
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Abstract
The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is disposed on a first die whereas the configuration memory is disposed on a second die. The second die is bonded to the first die in stacked relation. Each bit of configuration data passes from the second die to the first die through a pair of micropads. One micropad of the pair is disposed on the first die and the other micropad of the pair is disposed on the second die. When the first die and second die are brought together in face-to-face relation, the two micropads form an electrical connection through which the configuration data bit passes from the second die to the first die.
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