Signal processing device, signal processing method, delta-sigma modulation type fractional division PLL frequency synthesizer, radio communication device, delta-sigma modulation type D/A converter
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United States of America Patent
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Jul 12, 2005
Grant Date -
Jan 27, 2005
app pub date -
Aug 27, 2003
filing date -
Sep 5, 2002
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A fractional frequency divider (28) includes a latch (31) for holding frequency division data, a ΔΣ modulator (33), a digital dither circuit (32) for receiving a digital input F representing fraction part of the frequency division data from the latch (31) and supplying a digital output alternately changing between F+k and F-;k (where k is an integer) or a F value itself to the ΔΣ modulator (33), and circuit means (34 through 38) for executing fractional frequency division based on integer part (M value) of the frequency division data and an output of the ΔΣ modulator (33). The digital dither circuit (32) is useful for suppressing a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the ΔΣ modulator (33) receives a particular F value (e.g., F=2n-;1).
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