Method, architecture and circuitry for controlling pulse width in a phase and/or frequency detector
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United States of America Patent
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Jul 12, 2005
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N/A
app pub date -
Sep 24, 1999
filing date -
Sep 24, 1999
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Abstract
An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a parallel output data signal in response to (i) a first clock signal and (ii) one or more serial data signals. The second circuit may be configured to present the one or more serial data signals and the first clock signal in response to (i) a second clock signal and (ii) a parallel input data signal.
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