Locked loop circuit with clock hold function
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United States of America Patent
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Jul 26, 2005
Grant Date -
Mar 4, 2004
app pub date -
Feb 25, 2003
filing date -
Sep 3, 2002
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the phase mixing circuit generates a first clock signal having a phase angle according to the selected phase value. The hold signal generator asserts a hold signal in response to a transition of the select signal, and the latch circuit latches the state of the first clock signal in response to assertion of the hold signal.
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