Semiconductor package
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United States of America Patent
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Aug 2, 2005
Grant Date -
Jul 10, 2003
app pub date -
Dec 23, 2002
filing date -
Jan 9, 2002
priority date (Note) -
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status (Latency Note)
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Abstract
The present invention discloses a semiconductor package, wherein several chips can be packed thereinto. The present invention uses under bump metallurgies or bonding wires to connect the associated circuits of at least two chips in serial or in parallel. At least one slicing path is located between the at least two chips and a substrate is provided with an upper surface and a lower surface in which the upper surface is flip-chip bonded with the at least two chips.
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