Method, apparatus and computer program product for efficient per thread performance information
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United States of America Patent
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Aug 2, 2005
Grant Date -
Apr 21, 2005
app pub date -
Oct 16, 2003
filing date -
Oct 16, 2003
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A value in a counter on a processor is incremented for occurrences of a monitored event, providing a measured value for the event. The value of the counter register for a first thread is saved responsive to a switch from the first thread to a second thread. The value is saved in an accumulator in system memory. Then, responsive to a switch back to the first thread, the value for the first thread is restored from the accumulator. In this way, a counter may be read, and its value, for the first thread, for example, remains consistent despite any intervening thread switches. Since the counter register may be read directly, in the user state, this provides a faster and more consistent way to update performance counts.
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