Semiconductor package exhibiting efficient lead placement
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United States of America Patent
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Aug 9, 2005
Grant Date -
N/A
app pub date -
Mar 7, 2003
filing date -
Mar 7, 2003
priority date (Note) -
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Abstract
A semiconductor package exhibiting efficient placement of semiconductor leads in a micro lead frame design is provided. An integrated circuit die is bonded to the top surfaces of leads, thereby allowing the leads to partially reside under the die. As a result, surface area on the bottom surface of the semiconductor package is recaptured. The die can be further bonded a die paddle if so desired. One or more channels can be cut into the bottom surface of the package in order to separate first and second leads. Such channels allow separate leads to be fabricated from a single lead member which is subsequently cut.
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