Semidigital delay-locked loop using an analog-based finite state machine
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United States of America Patent
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Aug 9, 2005
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May 5, 2005
app pub date -
Oct 29, 2003
filing date -
Oct 29, 2003
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Abstract
A low-power full-rate semidigital DLL architecture using an analog-based FSM (AFSM). The AFSM is a mixed-mode FSM in which analog integration is substituted for digital filtering, thus enabling a lower power implementation of the clock and data recovery function. An integrated voltage is converted to a digital code by an analog-to-digital converter (ADC), and the digital code is used either directly or after (low frequency) digital signal processing to control a controllable delay element, such as, a phase rotator, for data edge tracking.
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