Algorithms tunning for dynamic lot dispatching in wafer and chip probing
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United States of America Patent
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Aug 16, 2005
Grant Date -
Mar 31, 2005
app pub date -
Sep 26, 2003
filing date -
Sep 26, 2003
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Abstract
A method and system for flexible, comprehensive, on-line, real-time dynamic lot dispatching in a semiconductor test foundry based on a two-phased, event-driven dispatching system structure. An adjustable priority formula and tuned algorithms integrated with PROMIS' constraint function give a nearly optimum dispatching list on any tester at any time with reduced mistake operations. Exception rules take care of special events to improve daily dispatching manual effort. This invention can automatically dispatch engineering lots according to engineering lots' capacity of Testing, solve conflict between wafer and package lots, efficiently reduce tester setup times, replace daily manual-dispatching sheet and keep a high CLIP rate while fully following MPS.
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